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Alsyl Enriquez

Alsyl Enriquez

Electrical Engineering at UC San Diego

From atoms to ASICs.

I've fabricated photonic and semiconductor devices at Harvard and Stanford, grown and characterized doped epitaxial films at Applied Materials, and planned a 3nm ASIC’s path to mass production at Marvell.

See my work

300 mm wafer, rendered in code.

The highlights.

Marvell · 2026

3nm

Next-gen hyperscaler switch ASIC. I built the product engineering plan that maps its path to mass production.

Published.

Co-author in Optica, 2026. Dynamic control of intrinsic optical chirality via MEMS-integrated photonic crystals, from my summer in Harvard's Mazur Group.

Read the paper

Si · SiGe · Ge · SiGeBC

Epitaxial films I ran baseline recipes for on Centura RPCVD tools at Applied Materials.

6

Internships across research labs and industry since 2022.

3

Cleanrooms. Stanford, Harvard, and UC San Diego.

Overview

Every stage of a chip's life.

Chips pass through many hands before they ship. I've worked at five of those stages, from simulation to production test.

  1. Simulate

    Harvard · Capasso Group

    FDTD · MATLAB

  2. Fabricate

    Stanford SNF · Harvard Mazur Group

    E-beam · RIE · DRIE

  3. Grow

    Applied Materials

    RPCVD epitaxy

  4. Measure

    Qualcomm Institute · Applied Materials

    SEM · XRD · JMP

  5. Test & ship

    Marvell

    WS · SLT · ATE · MPR

Industry

Two summers inside the semiconductor industry.

One in equipment R&D, growing and measuring epitaxial films. One in product engineering, getting a 3nm ASIC ready for volume.

Marvell Technology · Summer 2026

Taking 3nm to production.

Product Engineering Intern, Hyperscaler ASIC & Custom Compute.

  • 3nm switch ASIC
  • Wafer sort + system-level test
  • Reusable NPI template

Try it · Plan a path to mass production

Mass production releaseWeek 20On plan

Critical path: WS → SLT → HVM

What if

Drag a bar to delay it, or drag its right edge to change its length. Illustrative schedule, not Marvell data.

Applied Materials · Summer 2025

Finding flaws in near‑perfect crystals.

Process Engineering Intern, Silicon Epitaxy R&D.

  • XRD rocking curves & RSM
  • Python TDD calculator
  • DOE in JMP

Try it · Grow a SiGe film on silicon

Fully strained
Lattice mismatch
1.04%
Critical thickness
8.9 nm
Strain relaxed
70%
FWHM
504″482″ thickness · 147″ defects
Threading dislocations
8.2 × 10⁷ cm⁻²
25%
40 nm

Drag the crystal to pan. Model: Dismukes lattice constants, Matthews–Blakeslee critical thickness (the equilibrium limit; films grown at low temperature can stay strained longer), (004) rocking-curve broadening from film thickness and from dislocations via D = β²/4.35b². Dislocation density follows the typical range for SiGe grown directly on Si. Strain drawn ×10.

Research

Cleanroom research.

Four labs on two coasts, from Stanford's shared cleanroom to Harvard's photonics groups.

Harvard SEAS · Mazur Group · 2024

Twisted bilayer photonic crystals.

Stanford Nanofabrication Facility · 2022–24

Two years in Stanford's cleanroom.

Harvard SEAS · Capasso Group · 2023

Bending light the other way.

UC San Diego · Qualcomm Institute · 2024–25

Imaging devices at the nanoscale.

Try it

Twist the lattice.

In the Mazur Group, I fabricated twisted bilayer photonic crystals: two silicon nitride slabs patterned with a square lattice of holes, stacked as little as 360 nm apart. Twisting one against the other breaks their mirror symmetry, so the device transmits left- and right-handed light differently.

Our Optica paper tunes that twist with MEMS actuators, swinging circular dichroism from −0.85 to 0.64. Drag the lattice to try it.

θ = 10.39°moiré period = 6.74 µm (5.5a)device range

Blue band: the device's 9°–13° MEMS range. Geometry only, not an optics simulation.

Recognition

Papers, talks, and press.

Where my work has been published, presented, and featured.

Talks and program profiles

Talks

  • Fabrication of Twisted Bilayer Photonic Crystals

    2024 NNCI REU Convocation · University of Nebraska–Lincoln

    Watch
  • TechConnect World Innovation Conference & Expo

    Capasso Group metamaterial research · Washington, DC · 2024

  • Harvard Summer Research Symposium

    Poster and talk on ENZ metamaterials · Cambridge · 2023

Program profiles

  • Harvard SEAS REU

    2024 participant · Mazur Group

    View
  • Harvard MRSEC REU

    2023 participant · Capasso Group

    View
  • nano@stanford intern alumni

    Stanford Nanofabrication Facility · 2022–24

    View

About

I'm a first-generation college student from Hayward, California. I started at Chabot College, transferred to UC San Diego to study electrical engineering, and since 2022 I've spent my summers making, measuring, and testing semiconductor devices. That range gives me a working view of the full chip lifecycle, from the cleanroom to the test floor.

Studying

B.S. in Electrical Engineering at UC San Diego, Devices and Materials depth, expected June 2028. Associate's degree in Electrical and Electronics Engineering from Chabot College. Member of IEEE and the Vietnamese Student Association.

Looking for

Summer 2027 internships in hardware, operations, and process engineering.

Long term

Semiconductors, photonics, and quantum computing. Eventually, a company of my own.

Off the clock

Weightlifting, badminton, hiking, photography, and EDM concerts.

Technical Skills

  • E-beam lithography
  • RIE · DRIE
  • RPCVD epitaxy
  • SEM
  • XRD
  • ATE · SmarTest 8
  • JMP · DOE
  • Python
  • MATLAB
  • Verilog

Get in touch.

Feel free to message me. LinkedIn is the best way to reach me.

LinkedIn

linkedin.com/in/alsyl

Connect on LinkedIn

Email

[email protected]

Résumé

Updated October 2026